Implementación de un detector de promediación de clutter(CA-CFAR) usando VHDL
Abstract
Los detectores de radar son los encargados de tomar la decisión sobre la presencia o no de un blanco, realizando la discriminación del clutter que es una señal interferente. Con el objetivo de crear una base comparativa para implementaciones más complejas, los autores construyen el esquema clásico de detección CA-CFAR usando VHDL. Este lenguaje permite colocar la arquitectura diseñada en una tarjeta FPGA para su posterior aplicación en ambientes operacionales, lográndose así una solución de costo reducido. El correcto funcionamiento del esquema se probó comparando simulaciones realizadas en Quartus II 9.1 bajo clutterWeibull con las ya disponibles de una arquitectura similar en MATLAB.Downloads
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Published
2016-11-02
How to Cite
Machado Fermández, J. R., & Sánchez Rams, R. carlos. (2016). Implementación de un detector de promediación de clutter(CA-CFAR) usando VHDL. Telemática, 15(2), 52–61. Retrieved from https://revistatelematica.cujae.edu.cu/index.php/tele/article/view/228
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